Many modern computer systems include a virtual address space and a physical address space. Furthermore, a translation scheme is provided to translate a virtual address to a physical address such that data referenced by a virtual address and residing in the physical memory may be fetched by translating the virtual address into a corresponding physical address. For example, the virtual memory space can be based upon the concept that the computer system has a single, large memory space equal to the total capacity of the auxiliary memory of the computer system. All application programs to be processed by the computer system are constructed with reference to the virtual memory space by use of virtual addresses which define the location of instructions and data required by the program within the virtual memory space. When a particular application program is being executed by the central processing unit or units of the computer system, the data and instructions related to the program are transferred from the auxiliary memory devices of the system, as for example, from magnetic disks, and into the main physical memory of the system. The computer system is provided with a mechanism to dynamically translate the virtual addresses generated by the program being executed into correct main memory locations, each defined by a unique physical address.
During the execution of the program, the central processing unit continues to reference data and instructions by virtual addresses and a translation mechanism must be coupled between the central processing unit and the main physical memory to continuously translate the virtual addresses produced by the central processing unit into the corresponding physical addresses where the data or instructions may be found in the main physical memory. Typically, the virtual memory space is divided into memory units called pages. A page contains a predetermined number of basic addressable units. For example, the basic addressable unit may an 8-bit byte and a page may contain 512 bytes. The format for a virtual address to uniquely identify a basic addressable unit would be the virtual page number containing the addressable unit and the byte number of the addressable unit within the specified page.
A page table is maintained in the physical memory to cross reference virtual addresses to physical addresses. As the computer system dynamically transfers data to and from auxiliary memory devices, it generates page frame numbers which define 512 byte pages of physical memory, to be used on references to the virtual addresses. A page table entry is provided for each virtual page then residing in physical memory. The page frame number assigned to a particular virtual page at the time of a transfer of the related data from auxiliary memory to main memory is stored in the page table entry for that virtual page.
Accordingly, in concept, a physical address corresponding to a particular virtual address can be obtained by fetching the page table entry for the virtual page of that virtual address from physical memory and merging the byte number of the addressable unit of data with the page frame number contained in the page table entry. However, in practice, the central processing unit maintains a translation buffer that is a special purpose cache of recently used page table entries. Most often, the translation buffer already contains the page table entries for the virtual addresses being used by a program and the processor need not go to physical memory to obtain them.
In known computer systems, the translation buffer is in a translation mechanism that is coupled on a timing-critical data path between the central processing unit and the main memory. The translation mechanism ascertains the page frame number for the virtual page number of the virtual address to be translated from the translation buffer and attaches the byte number of the virtual address to the page frame number listed in the translation buffer to provide the physical address. The output of the translation mechanism is typically coupled to one input of a multiplexer. The other input of the multiplexer is coupled directly to the central processing unit to provide a bypass line around the translation mechanism. The output of the multiplexer is then coupled to the main memory. In this manner, either a physical address determined by the translation mechanism or an address directly generated by the central processing unit can be transmitted to the main memory.
As indicated above, most virtual to physical address translations are performed through use of the translation buffer. However, if there is a miss, i.e., the translation buffer does not contain a virtual page number entry for the virtual address to be translated, then the page table entry for the virtual address to be translated must be fetched from physical memory to load the translation buffer- In the heretofore known computer systems, the physical base address of the page table is held in a register. The processor executes a translation algorithm utilizing the physical base address stored in the register and the virtual page number of the virtual address to be translated to calculate the physical address of the page table entry needed for the translation. This enables the processor to directly fetch the page table entry via the translation mechanism bypass line. The page frame number of the page table entry is then loaded into the translation buffer by the central processing unit as an entry corresponding to the virtual page number of the original virtual address to be translated. The translation mechanism can then complete the translation by attaching the byte number of the virtual address to the page frame number loaded into the translation buffer by the central processing unit.